In the fabrication of semiconductor devices that include an integrated circuit, such as electronic signal processors, memory devices, and photoactive devices (e.g., light-emitting devices (LEDs), laser diodes, photocells, photodetectors, etc.), it is often desirable to employ what is referred to in the art as an “interposer” between two devices (e.g., between two integrated circuit devices), between a device and a structure (e.g., between an integrated circuit device and a package substrate, such as a circuit board or layer), or between two structures. The interposer is disposed between the two devices and/or structures, and may be used to provide a structural and electrical interconnection between the two devices and/or structures.
In some cases, the interposer may be used to redistribute an electrical connection pattern. For example, an integrated circuit device may have an array of electrical contact features arranged in a first pattern, and another device or structure to which the integrated circuit device is to be coupled may have an array of electrical contact features arranged in a different, second pattern. Thus, the integrated circuit device cannot simply be abutted against and bonded to the another device or structure to establish electrical connection between the electrical contact features of the integrated circuit device and the electrical contact features of the another device or structure.
To facilitate the electrical interconnection, an interposer may be fabricated that includes a first set of electrical contact features on a first side thereof arranged in a pattern that is a mirror image of the pattern of the electrical contact features of the integrated circuit device, and a second set of electrical contact features on an opposing second side thereof arranged in a different pattern that is a mirror image of the pattern of the electrical contact features of the another device or structure. The interposer may comprise one or more of electrically conductive vias that extend vertically through at least a portion of the interposer perpendicular to the major plane of the interposer, electrically conductive traces that extend horizontally across the interposer parallel to the major plane of the interposer, and electrically conductive contact pads, which define the locations at which electrical contact is to be established with the integrated circuit device and the another device or structure. The conductive vias and traces may be used to “redistribute” the pattern of the contact pads on the first side of the interposer to a different pattern of the contact pads on the opposing second side of the interposer. In this configuration, the contact pads on the first side of the interposer may be structurally and electrically coupled to the electrical contact features of the integrated circuit device, and the contact pads on the opposing second side of the interposer may be structurally and electrically coupled to the electrical contact features of the another structure or device, thereby providing an electrical interconnection between the integrated circuit device and the another structure or device through the interposer.
Interposers are commonly relatively thick so as to enable handling and manipulation of the interposers by common semiconductor fabrication processing equipment. For example, interposers may have an average layer thickness of two hundred microns (200 μm) or more.
The features of semiconductor devices continue to scale downward to smaller dimensions. As the average cross-sectional dimension (e.g., the average diameter) of conductive vias formed through interposers are decreased, the aspect ratios of the conductive vias increases. The aspect ratio of a conductive via is defined as the length of the conductive via (in the vertical dimension perpendicular to the major plane of the interposer) divided by the average cross-sectional dimension of the conductive via. For example, a conductive via having a length of two hundred microns (200 μm) and an average cross-sectional dimension of forty microns (40 μm) has an aspect ratio of five (5) (i.e., 200/40=5).
Conductive vias having high aspect ratios are difficult to form. To form conductive vias in interposers, holes may be first formed through the interposer and subsequently filled with conductive metal using one or more plating processes (e.g., a first electroless plating process followed by an electrolytic plating process). Holes having high aspect ratios are difficult to fill with the metal in the plating process due to the need to deposit metal with good step coverage and free of voids. For example, the regions in the holes proximate the opposing major surfaces of the interposer may become plugged with metal prior to completely filling the region of the hole near the center of the interposer, thereby preventing further deposition of metal within the hole and resulting in voids within the resulting conductive via. Such voids can render the conductive vias inoperable. Also, larger conductive vias require the use of more metal, which adds to cost and increases the duration of the metal deposition process. Larger conductive vias also occupy more area on the interposer, which limits the number of conductive vias that may be formed in a given area of the interposer, which may limit the overall operational bandwidth of any semiconductor device such as an interposer.